System and method for using a plurality of heterogeneous processors in a common computer system

ABSTRACT

A system for using a plurality of heterogeneous processors in a common computer system is presented. Each processor type in the heterogeneous group handles a particular instruction set. The processors share a common memory using a common bus. In one embodiment, one of the processor types accesses the memory using DMA instructions. In another embodiment, a cache for each type of processor is stored in the common memory pool. In one embodiment, one or more PowerPC processors shares a memory with one or more Synergistic Processing Complex (SPC). A common table is used to track and maintain memory for the various processors.

RELATED APPLICATIONS

This application is a continuation-in-part of co-pending U.S.Non-Provisional patent application Ser. No. 09/816,004, entitled“COMPUTER ARCHITECTURE AND SOFTWARE CELLS FOR BROADBAND NETWORKS,”filing date Mar. 22, 2001, which is incorporated herein by reference, inits entirety.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates in general to a system for using aplurality of heterogeneous processors in a common computer system. Moreparticularly, the present invention relates to a system for embedding aplurality of heterogeneous processors on a substrate that share a commonmemory.

2. Description of the Related Art

Electronics are becoming more and more complex. Many consumerelectronics today perform computations that only large computer systemsuse to perform. The demand for consumer electronics has fueledelectronic designers and manufacturers to continue to evolve and improveintegrated circuits (IC's) that are used in consumer electronics.

Processor technology, in particular, has benefited from consumer demand.Different types of processors have evolved that focus on particularfunctions, or computations. For example, a microprocessor is bestutilized for control functions whereas a digital signal processor (DSP)is best utilized for high-speed signal manipulation calculations. Achallenge found is that many electronic devices perform a variety offunctions which requires more than one processor type. For example, acell phone uses a microprocessor for command and control signalingbetween a base station whereas the cell phone uses a digital signalprocessor for cellular signal manipulation, such as decoding,encrypting, and chip rate processing.

A processor typically has dedicated memory that the processor uses tostore and retrieve data. An IC designer attempts to provide a processorwith as much dedicated memory as possible so the processor is not memoryresource limited. A challenge found with integrating multipleprocessors, however, is that each processor has dedicated memory that isnot shared with other processors, even if a particular processor doesnot use portions of its dedicated memory. For example, a processor mayhave 10 MB of dedicated memory whereby the processors uses 6 MB for datastorage and retrieval. In this example, the processor's 4 MB of unusedmemory is not accessible by other processors which equates to anunderutilization of memory.

What is needed, therefore, is a system for integrating a heterogeneousgroup of processors in conjunction with maximizing memory utilization.

SUMMARY

It has been discovered that the aforementioned challenges are resolvedby including a heterogeneous group of processors in an integratedcircuit (IC) that shares a common memory map. Each processor type in theheterogeneous group handles a particular instruction set and theprocessors share a common memory using a common bus. A common memory mapis used to track and maintain memory for the various processors.

The IC is segmented into a control plane and a data plane. The controlplane includes a main processor that runs an operating system. Forexample, the control plane may include a PowerPC based processor thatruns a Linux operating system. The main processor also manages a commonmemory map table that is used to manage non-private memory areas withinthe IC.

The data plane includes Synergistic Processing Complex's (SPC's) wherebyeach SPC is used to process data information. For example, a device mayhave four SPC's and each SPC may be responsible for separate processingtasks, such as modulation, chip rate processing, encoding, and networkinterfacing. In another example, each SPC may have identical instructionsets and may be used in parallel to perform operations benefiting fromparallel processes.

Each SPC includes a synergistic processing unit (SPU) which is aprocessing core, such as a digital signal processor, a microcontroller,a microprocessor, or a combination of these cores. Each SPC alsoincludes a local storage area which is divided into a private memoryarea and a non-private memory area. The private memory area isaccessible by a corresponding SPU and the non-private memory area ismanaged by the common memory map and is accessible by each processorwithin the IC.

The foregoing is a summary and thus contains, by necessity,simplifications, generalizations, and omissions of detail; consequently,those skilled in the art will appreciate that the summary isillustrative only and is not intended to be in any way limiting. Otheraspects, inventive features, and advantages of the present invention, asdefined solely by the claims, will become apparent in the non-limitingdetailed description set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerousobjects, features, and advantages made apparent to those skilled in theart by referencing the accompanying drawings. The use of the samereference symbols in different drawings indicates similar or identicalitems.

FIG. 1 illustrates the overall architecture of a computer network inaccordance with the present invention;

FIG. 2 is a diagram illustrating the structure of a processing unit (PU)in accordance with the present invention;

FIG. 3 is a diagram illustrating the structure of a broadband engine(BE) in accordance with the present invention;

FIG. 4 is a diagram illustrating the structure of an synergisticprocessing unit (SPU) in accordance with the present invention;

FIG. 5 is a diagram illustrating the structure of a processing unit,visualizer (VS) and an optical interface in accordance with the presentinvention;

FIG. 6 is a diagram illustrating one combination of processing units inaccordance with the present invention;

FIG. 7 illustrates another combination of processing units in accordancewith the present invention;

FIG. 8 illustrates yet another combination of processing units inaccordance with the present invention;

FIG. 9 illustrates yet another combination of processing units inaccordance with the present invention;

FIG. 10 illustrates yet another combination of processing units inaccordance with the present invention;

FIG. 11A illustrates the integration of optical interfaces within a chippackage in accordance with the present invention;

FIG. 11B is a diagram of one configuration of processors using theoptical interfaces of FIG. 11A;

FIG. 11C is a diagram of another configuration of processors using theoptical interfaces of FIG. 11A;

FIG. 12A illustrates the structure of a memory system in accordance withthe present invention;

FIG. 12B illustrates the writing of data from a first broadband engineto a second broadband engine in accordance with the present invention;

FIG. 13 is a diagram of the structure of a shared memory for aprocessing unit in accordance with the present invention;

FIG. 14A illustrates one structure for a bank of the memory shown inFIG. 13;

FIG. 14B illustrates another structure for a bank of the memory shown inFIG. 13;

FIG. 15 illustrates a structure for a direct memory access controller inaccordance with the present invention;

FIG. 16 illustrates an alternative structure for a direct memory accesscontroller in accordance with the present invention;

FIGS. 17-31 illustrate the operation of data synchronization inaccordance with the present invention;

FIG. 32 is a three-state memory diagram illustrating the various statesof a memory location in accordance with the data synchronization schemeof the-present invention;

FIG. 33 illustrates the structure of a key control table for a hardwaresandbox in accordance with the present invention;

FIG. 34 illustrates a scheme for storing memory access keys for ahardware sandbox in accordance with the present invention;

FIG. 35 illustrates the structure of a memory access control table for ahardware sandbox in accordance with the present invention;

FIG. 36 is a flow diagram of the steps for accessing a memory sandboxusing the key control table of FIG. 33 and the memory access controltable of FIG. 35;

FIG. 37 illustrates the structure of a software cell in accordance withthe present invention;

FIG. 38 is a flow diagram of the steps for issuing remote procedurecalls to SPUs in accordance with the present invention;

FIG. 39 illustrates the structure of a dedicated pipeline for processingstreaming data in accordance with the present invention;

FIG. 40 is a flow diagram of the steps performed by the dedicatedpipeline of FIG. 39 in the processing of streaming data in accordancewith the present invention;

FIG. 41 illustrates an alternative structure for a dedicated pipelinefor the processing of streaming data in accordance with the presentinvention;

FIG. 42 illustrates a scheme for an absolute timer for coordinating theparallel processing of applications and data by SPUs in accordance withthe present invention;

FIG. 43 is a diagram showing a processor element architecture whichincludes a plurality of heterogeneous processors;

FIG. 44A is a diagram showing a device that uses a common memory map toshare memory between heterogeneous processors;

FIG. 44B is a diagram showing a local storage area divided into privatememory and non-private memory;

FIG. 45 is a flowchart showing steps taken in configuring local memorylocated in a synergistic processing complex;

FIG. 46A is a diagram showing a central device with predefinedinterfaces connected to two peripheral devices;

FIG. 46B is a diagram showing two peripheral devices connected to acentral device with mismatching input and output interfaces;

FIG. 47A is a diagram showing a device with dynamic interfaces that isconnected to a first set of peripheral devices;

FIG. 47B is a diagram showing a central device with dynamic interfacesthat has re-allocated pin assignments in order to match two newlyconnected peripheral devices;

FIG. 48 is a flowchart showing steps taken in a device configuring itsdynamic input and output interfaces based upon peripheral devices thatare connected to the device;

FIG. 49A is a diagram showing input pin assignments for swizel logiccorresponding to two input controllers;

FIG. 49B is a diagram showing output pin assignments for flexibleinput-output logic corresponding to two output controllers; and

FIG. 50 is a diagram showing a flexible input-output logic embodiment.

DETAILED DESCRIPTION

The following is intended to provide a detailed description of anexample of the invention and should not be taken to be limiting of theinvention itself. Rather, any number of variations may fall within thescope of the invention which is defined in the claims following thedescription.

The overall architecture for a computer system 101 in accordance withthe present invention is shown in FIG. 1. As illustrated in this figure,system 101 includes network 104 to which is connected a plurality ofcomputers and computing devices. Network 104 can be a LAN, a globalnetwork, such as the Internet, or any other computer network.

The computers and computing devices connected to network 104 (thenetwork's “members”) include, e.g., client computers 106, servercomputers 108, personal digital assistants (PDAs) 110, digitaltelevision (DTV) 112 and other wired or wireless computers and computingdevices. The processors employed by the members of network 104 areconstructed from the same common computing module. These processors alsopreferably all have the same ISA and perform processing in accordancewith the same instruction set. The number of modules included within anyparticular processor depends upon the processing power required by thatprocessor.

For example, since servers 108 of system 101 perform more processing ofdata and applications than clients 106, servers 108 contain morecomputing modules than clients 106. PDAs 110, on the other hand, performthe least amount of processing. PDAs 110, therefore, contain thesmallest number of computing modules. DTV 112 performs a level ofprocessing between that of clients 106 and servers 108. DTV 112,therefore, contains a number of computing modules between that ofclients 106 and servers 108. As discussed below, each computing modulecontains a processing controller and a plurality of identical processingunits for performing parallel processing of the data and applicationstransmitted over network 104.

This homogeneous configuration for system 101 facilitates adaptability,processing speed and processing efficiency. Because each member ofsystem 101 performs processing using one or more (or some fraction) ofthe same computing module, the particular computer or computing deviceperforming the actual processing of data and applications isunimportant. The processing of a particular application and data,moreover, can be shared among the network's members. By uniquelyidentifying the cells comprising the data and applications processed bysystem 101 throughout the system, the processing results can betransmitted to the computer or computing device requesting theprocessing regardless of where this processing occurred. Because themodules performing this processing have a common structure and employ acommon ISA, the computational burdens of an added layer of software toachieve compatibility among the processors is avoided. This architectureand programming model facilitates the processing speed necessary toexecute, e.g., real-time, multimedia applications.

To take further advantage of the processing speeds and efficienciesfacilitated by system 101, the data and applications processed by thissystem are packaged into uniquely identified, uniformly formattedsoftware cells 102. Each software cell 102 contains, or can contain,both applications and data. Each software cell also contains an ID toglobally identify the cell throughout network 104 and system 101. Thisuniformity of structure for the software cells, and the software cells'unique identification throughout the network, facilitates the processingof applications and data on any computer or computing device of thenetwork. For example, a client 106 may formulate a software cell 102but, because of the limited processing capabilities of client 106,transmit this software cell to a server 108 for processing. Softwarecells can migrate, therefore, throughout network 104 for processing onthe basis of the availability of processing resources on the network.

The homogeneous structure of processors and software cells of system 101also avoids many of the problems of today's heterogeneous networks. Forexample, inefficient programming models which seek to permit processingof applications on any ISA using any instruction set, e.g., virtualmachines such as the Java virtual machine, are avoided. System 101,therefore, can implement broadband processing far more effectively andefficiently than today's networks.

The basic processing module for all members of network 104 is theprocessing unit (PU). FIG. 2 illustrates the structure of a PU. As shownin this figure, PE 201 comprises a processing unit (PU) 203, a directmemory access controller (DMAC) 205 and a plurality of synergisticprocessing units (SPUs), namely, SPU 207, SPU 209, SPU 211, SPU 213, SPU215, SPU 217, SPU 219 and SPU 221. A local PE bus 223 transmits data andapplications among the SPUs, DMAC 205 and PU 203. Local PE bus 223 canhave, e.g., a conventional architecture or be implemented as a packetswitch network. Implementation as a packet switch network, whilerequiring more hardware, increases available bandwidth.

PE 201 can be constructed using various methods for implementing digitallogic. PE 201 preferably is constructed, however, as a single integratedcircuit employing a complementary metal oxide semiconductor (CMOS) on asilicon substrate. Alternative materials for substrates include galliumarsinide, gallium aluminum arsinide and other so-called III-B compoundsemploying a wide variety of dopants. PE 201 also could be implementedusing superconducting material, e.g., rapid single-flux-quantum (RSFQ)logic.

PE 201 is closely associated with a dynamic random access memory (DRAM)225 through a high bandwidth memory connection 227. DRAM 225 functionsas the main memory for PE 201. Although a DRAM 225 preferably is adynamic random access memory, DRAM 225 could be implemented using othermeans, e.g., as a static random access memory (SRAM), a magnetic randomaccess memory (MRAM), an optical memory or a holographic memory. DMAC205 facilitates the transfer of data between DRAM 225 and the SPUs andPU of PE 201. As further discussed below, DMAC 205 designates for eachSPU an exclusive area in DRAM 225 into which only the SPU can write dataand from which only the SPU can read data. This exclusive area isdesignated a “sandbox.”

PU 203 can be, e.g., a standard processor capable of stand-aloneprocessing of data and applications. In operation, PU 203 schedules andorchestrates the processing of data and applications by the SPUs. TheSPUs preferably are single instruction, multiple data (SIMD) processors.Under the control of PU 203, the SPUs perform the processing of thesedata and applications in a parallel and independent manner. DMAC 205controls accesses by PU 203 and the SPUs to the data and applicationsstored in the shared DRAM 225. Although PE 201 preferably includes eightSPUs, a greater or lesser number of SPUs can be employed in a PUdepending upon the processing power required. Also, a number of PUs,such as PE 201, may be joined or packaged together to provide enhancedprocessing power.

For example, as shown in FIG. 3, four PUs may be packaged or joinedtogether, e.g., within one or more chip packages, to form a singleprocessor for a member of network 104. This configuration is designateda broadband engine (BE). As shown in FIG. 3, BE 301 contains four PUs,namely, PE 303, PE 305, PE 307 and PE 309. Communications among thesePUs are over BE bus 311. Broad bandwidth memory connection 313 providescommunication between shared DRAM 315 and these PUs. In lieu of BE bus311, communications among the PUs of BE 301 can occur through DRAM 315and this memory connection.

Input/output (I/O) interface 317 and external bus 319 providecommunications between broadband engine 301 and the other members ofnetwork 104. Each PU of BE 301 performs processing of data andapplications in a parallel and independent manner analogous to theparallel and independent processing of applications and data performedby the SPUs of a PU.

FIG. 4 illustrates the structure of an SPU. SPU 402 includes localmemory 406, registers 410, four floating point units 412 and fourinteger units 414. Again, however, depending upon the processing powerrequired, a greater or lesser number of floating points units 412 andinteger units 414 can be employed. In a preferred embodiment, localmemory 406 contains 128 kilobytes of storage, and the capacity ofregisters 410 is 128.times. 128 bits. Floating point units 412preferably operate at a speed of 32 billion floating point operationsper second (32 GFLOPS), and integer units 414 preferably operate at aspeed of 32 billion operations per second (32 GOPS).

Local memory 406 is not a cache memory. Local memory 406 is preferablyconstructed as an SRAM. Cache coherency support for an SPU isunnecessary. A PU may require cache coherency support for direct memoryaccesses initiated by the PU. Cache coherency support is not required,however, for direct memory accesses initiated by an SPU or for accessesfrom and to external devices.

SPU 402 further includes bus 404 for transmitting applications and datato and from the SPU. In a preferred embodiment, this bus is 1,024 bitswide. SPU 402 further includes internal busses 408, 420 and 418. In apreferred embodiment, bus 408 has a width of 256 bits and providescommunications between local memory 406 and registers 410. Busses 420and 418 provide communications between, respectively, registers 410 andfloating point units 412, and registers 410 and integer units 414. In apreferred embodiment, the width of busses 418 and 420 from registers 410to the floating point or integer units is 384 bits, and the width ofbusses 418 and 420 from the floating point or integer units to registers410 is 128 bits. The larger width of these busses from registers 410 tothe floating point or integer units than from these units to registers410 accommodates the larger data flow from registers 410 duringprocessing. A maximum of three words are needed for each calculation.The result of each calculation, however, normally is only one word.

FIGS. 5-10 further illustrate the modular structure of the processors ofthe members of network 104. For example, as shown in FIG. 5, a processormay comprise a single PU 502. As discussed above, this PU typicallycomprises a PU, DMAC and eight SPUs. Each SPU includes local storage(LS). On the other hand, a processor may comprise the structure ofvisualizer (VS) 505. As shown in FIG. 5, VS 505 comprises PU 512, DMAC514 and four SPUs, namely, SPU 516, SPU 518, SPU 520 and SPU 522. Thespace within the chip package normally occupied by the other four SPUsof a PU is occupied in this case by pixel engine 508, image cache 510and cathode ray tube controller (CRTC) 504. Depending upon the speed ofcommunications required for PU 502 or VS 505, optical interface 506 alsomay be included on the chip package.

Using this standardized, modular structure, numerous other variations ofprocessors can be constructed easily and efficiently. For example, theprocessor shown in FIG. 6 comprises two chip packages, namely, chippackage 602 comprising a BE and chip package 604 comprising four VSs.Input/output (I/O) 606 provides an interface between the BE of chippackage 602 and network 104. Bus 608 provides communications betweenchip package 602 and chip package 604. Input output processor (IOP) 610controls the flow of data into and out of I/O 606. I/O 606 may befabricated as an application specific integrated circuit (ASIC). Theoutput from the VSs is video signal 612.

FIG. 7 illustrates a chip package for a BE 702 with two opticalinterfaces 704 and 706 for providing ultra high speed communications tothe other members of network 104 (or other chip packages locallyconnected). BE 702 can function as, e.g., a server on network 104.

The chip package of FIG. 8 comprises two PEs 802 and 804 and two VSs 806and 808. An I/O 810 provides an interface between the chip package andnetwork 104. The output from the chip package is a video signal. Thisconfiguration may function as, e.g., a graphics work station.

FIG. 9 illustrates yet another configuration. This configurationcontains one-half of the processing power of the configurationillustrated in FIG. 8. Instead of two PUs, one PE 902 is provided, andinstead of two VSs, one VS 904 is provided. I/O 906 has one-half thebandwidth of the I/O illustrated in FIG. 8. Such a processor also mayfunction, however, as a graphics work station.

A final configuration is shown in FIG. 10. This processor consists ofonly a single VS 1002 and an I/O 1004. This configuration may functionas, e.g., a PDA.

FIG. 11A illustrates the integration of optical interfaces into a chippackage of a processor of network 104. These optical interfaces convertoptical signals to electrical signals and electrical signals to opticalsignals and can be constructed from a variety of materials including,e.g., gallium arsinide, aluminum gallium arsinide, germanium and otherelements or compounds. As shown in this figure, optical interfaces 1104and 1106 are fabricated on the chip package of BE 1102. BE bus 1108provides communication among the PUs of BE 1102, namely, PE 1110, PE1112, PE 1114, PE 1116, and these optical interfaces. Optical interface1104 includes two ports, namely, port 1118 and port 1120, and opticalinterface 1106 also includes two ports, namely, port 1122 and port 1124.Ports 1118, 1120, 1122 and 1124 are connected to, respectively, opticalwave guides 1126, 1128, 1130 and 1132. Optical signals are transmittedto and from BE 1102 through these optical wave guides via the ports ofoptical interfaces 1104 and 1106.

A plurality of BEs can be connected together in various configurationsusing such optical wave guides and the four optical ports of each BE.For example, as shown in FIG. 1B, two or more BEs, e.g., BE 1152, BE1154 and BE 1156, can be connected serially through such optical ports.In this example, optical interface 1166 of BE 1152 is connected throughits optical ports to the optical ports of optical interface 1160 of BE1154. In a similar manner, the optical ports of optical interface 1162on BE 1154 are connected to the optical ports of optical interface 1164of BE 1156.

A matrix configuration is illustrated in FIG. 11C. In thisconfiguration, the optical interface of each BE is connected to twoother BEs. As shown in this figure, one of the optical ports of opticalinterface 1188 of BE 1172 is connected to an optical port of opticalinterface 1182 of BE 1176. The other optical port of optical interface1188 is connected to an optical port of optical interface 1184 of BE1178. In a similar manner, one optical port of optical interface 1190 ofBE 1174 is connected to the other optical port of optical interface 1184of BE 1178. The other optical port of optical interface 1190 isconnected to an optical port of optical interface 1186 of BE 1180. Thismatrix configuration can be extended in a similar manner to other BEs.

Using either a serial configuration or a matrix configuration, aprocessor for network 104 can be constructed of any desired size andpower. Of course, additional ports can be added to the opticalinterfaces of the BEs, or to processors having a greater or lessernumber of PUs than a BE, to form other configurations.

FIG. 12A illustrates the control system and structure for the DRAM of aBE. A similar control system and structure is employed in processorshaving other sizes and containing more or less PUs. As shown in thisfigure, a cross-bar switch connects each DMAC 1210 of the four PUscomprising BE 1201 to eight bank controls 1206. Each bank control 1206controls eight banks 1208 (only four are shown in the figure) of DRAM1204. DRAM 1204, therefore, comprises a total of sixty-four banks. In apreferred embodiment, DRAM 1204 has a capacity of 64 megabytes, and eachbank has a capacity of 1 megabyte. The smallest addressable unit withineach bank, in this preferred embodiment, is a block of 1024 bits.

BE 1201 also includes switch unit 1212. Switch unit 1212 enables otherSPUs on BEs closely coupled to BE 1201 to access DRAM 1204. A second BE,therefore, can be closely coupled to a first BE, and each SPU of each BEcan address twice the number of memory locations normally accessible toan SPU. The direct reading or writing of data from or to the DRAM of afirst BE from or to the DRAM of a second BE can occur through a switchunit such as switch unit 1212.

For example, as shown in FIG. 12B, to accomplish such writing, the SPUof a first BE, e.g., SPU 1220 of BE 1222, issues a write command to amemory location of a DRAM of a second BE, e.g., DRAM 1228 of BE 1226(rather than, as in the usual case, to DRAM 1224 of BE 1222). DMAC 1230of BE 1222 sends the write command through cross-bar switch 1221 to bankcontrol 1234, and bank control 1234 transmits the command to an externalport 1232 connected to bank control 1234. DMAC 1238 of BE 1226 receivesthe write command and transfers this command to switch unit 1240 of BE1226. Switch unit 1240 identifies the DRAM address contained in thewrite command and sends the data for storage in this address throughbank control 1242 of BE 1226 to bank 1244 of DRAM 1228. Switch unit1240, therefore, enables both DRAM 1224 and DRAM 1228 to function as asingle memory space for the SPUs of BE 1226.

FIG. 13 shows the configuration of the sixty-four banks of a DRAM. Thesebanks are arranged into eight rows, namely, rows 1302, 1304, 1306, 1308,1310, 1312, 1314 and 1316 and eight columns, namely, columns 1320, 1322,1324, 1326, 1328, 1330, 1332 and 1334. Each row is controlled by a bankcontroller. Each bank controller, therefore, controls eight megabytes ofmemory.

FIGS. 14A and 14B illustrate different configurations for storing andaccessing the smallest addressable memory unit of a DRAM, e.g., a blockof 1024 bits. In FIG. 14A, DMAC 1402 stores in a single bank 1404 eight1024 bit blocks 1406. In FIG. 14B, on the other hand, while DMAC 1412reads and writes blocks of data containing 1024 bits, these blocks areinterleaved between two banks, namely, bank 1414 and bank 1416. Each ofthese banks, therefore, contains sixteen blocks of data, and each blockof data contains 512 bits. This interleaving can facilitate fasteraccessing of the DRAM and is useful in the processing of certainapplications.

FIG. 15 illustrates the architecture for a DMAC 1504 within a PE. Asillustrated in this figure, the structural hardware comprising DMAC 1506is distributed throughout the PE such that each SPU 1502 has directaccess to a structural node 1504 of DMAC 1506. Each node executes thelogic appropriate for memory accesses by the SPU to which the node hasdirect access.

FIG. 16 shows an alternative embodiment of the DMAC, namely, anon-distributed architecture. In this case, the structural hardware ofDMAC 1606 is centralized. SPUs 1602 and PU 1604 communicate with DMAC1606 via local PE bus 1607. DMAC 1606 is connected through a cross-barswitch to a bus 1608. Bus 1608 is connected to DRAM 1610.

As discussed above, all of the multiple SPUs of a PU can independentlyaccess data in the shared DRAM. As a result, a first SPU could beoperating upon particular data in its local storage at a time duringwhich a second SPU requests these data. If the data were provided to thesecond SPU at that time from the shared DRAM, the data could be invalidbecause of the first SPU's ongoing processing which could change thedata's value. If the second processor received the data from the sharedDRAM at that time, therefore, the second processor could generate anerroneous result. For example, the data could be a specific value for aglobal variable. If the first processor changed that value during itsprocessing, the second processor would receive an outdated value. Ascheme is necessary, therefore, to synchronize the SPUs' reading andwriting of data from and to memory locations within the shared DRAM.This scheme must prevent the reading of data from a memory location uponwhich another SPU currently is operating in its local storage and,therefore, which are not current, and the writing of data into a memorylocation storing current data.

To overcome these problems, for each addressable memory location of theDRAM, an additional segment of memory is allocated in the DRAM forstoring status information relating to the data stored in the memorylocation. This status information includes a full/empty (F/E) bit, theidentification of an SPU (SPU ID) requesting data from the memorylocation and the address of the SPU's local storage (LS address) towhich the requested data should be read. An addressable memory locationof the DRAM can be of any size. In a preferred embodiment, this size is1024 bits.

The setting of the F/E bit to 1 indicates that the data stored in theassociated memory location are current. The setting of the F/E bit to 0,on the other hand, indicates that the data stored in the associatedmemory location are not current. If an SPU requests the data when thisbit is set to 0, the SPU is prevented from immediately reading the data.In this case, an SPU ID identifying the SPU requesting the data, and anLS address identifying the memory location within the local storage ofthis SPU to which the data are to be read when the data become current,are entered into the additional memory segment.

An additional memory segment also is allocated for each memory locationwithin the local storage of the SPUs. This additional memory segmentstores one bit, designated the “busy bit.” The busy bit is used toreserve the associated LS memory location for the storage of specificdata to be retrieved from the DRAM. If the busy bit is set to 1 for aparticular memory location in local storage, the SPU can use this memorylocation only for the writing of these specific data. On the other hand,if the busy bit is set to 0 for a particular memory location in localstorage, the SPU can use this memory location for the writing of anydata.

Examples of the manner in which the F/E bit, the SPU ID, the LS addressand the busy bit are used to synchronize the reading and writing of datafrom and to the shared DRAM of a PU are illustrated in FIGS. 17-31.

As shown in FIG. 17, one or more PUs, e.g., PE 1720, interact with DRAM1702. PE 1720 includes SPU 1722 and SPU 1740. SPU 1722 includes controllogic 1724, and SPU 1740 includes control logic 1742. SPU 1722 alsoincludes local storage 1726. This local storage includes a plurality ofaddressable memory locations 1728. SPU 1740 includes local storage 1744,and this local storage also includes a plurality of addressable memorylocations 1746. All of these addressable memory locations preferably are1024 bits in size.

An additional segment of memory is associated with each LS addressablememory location. For example, memory segments 1729 and 1734 areassociated with, respectively, local memory locations 1731 and 1732, andmemory segment 1752 is associated with local memory location 1750. A“busy bit,” as discussed above, is stored in each of these additionalmemory segments. Local memory location 1732 is shown with several Xs toindicate that this location contains data.

DRAM 1702 contains a plurality of addressable memory locations 1704,including memory locations 1706 and 1708. These memory locationspreferably also are 1024 bits in size. An additional segment of memoryalso is associated with each of these memory locations. For example,additional memory segment 1760 is associated with memory location 1706,and additional memory segment 1762 is associated with memory location1708. Status information relating to the data stored in each memorylocation is stored in the memory segment associated with the memorylocation. This status information includes, as discussed above, the F/Ebit, the SPU ID and the LS address. For example, for memory location1708, this status information includes F/E bit 1712, SPU ID 1714 and LSaddress 1716.

Using the status information and the busy bit, the synchronized readingand writing of data from and to the shared DRAM among the SPUs of a PU,or a group of PUs, can be achieved.

FIG. 18 illustrates the initiation of the synchronized writing of datafrom LS memory location 1732 of SPU 1722 to memory location 1708 of DRAM1702. Control 1724 of SPU 1722 initiates the synchronized writing ofthese data. Since memory location 1708 is empty, F/E bit 1712 is set to0. As a result, the data in LS location 1732 can be written into memorylocation 1708. If this bit were set to 1 to indicate that memorylocation 1708 is full and contains current, valid data, on the otherhand, control 1722 would receive an error message and be prohibited fromwriting data into this memory location.

The result of the successful synchronized writing of the data intomemory location 1708 is shown in FIG. 19. The written data are stored inmemory location 1708, and F/E bit 1712 is set to 1. This settingindicates that memory location 1708 is full and that the data in thismemory location are current and valid.

FIG. 20 illustrates the initiation of the synchronized reading of datafrom memory location 1708 of DRAM 1702 to LS memory location 1750 oflocal storage 1744. To initiate this reading, the busy bit in memorysegment 1752 of LS memory location 1750 is set to 1 to reserve thismemory location for these data. The setting of this busy bit to 1prevents SPU 1740 from storing other data in this memory location.

As shown in FIG. 21, control logic 1742 next issues a synchronize readcommand for memory location 1708 of DRAM 1702. Since F/E bit 1712associated with this memory location is set to 1, the data stored inmemory location 1708 are considered current and valid. As a result, inpreparation for transferring the data from memory location 1708 to LSmemory location 1750, F/E bit 1712 is set to 0. This setting is shown inFIG. 22. The setting of this bit to 0 indicates that, following thereading of these data, the data in memory location 1708 will be invalid.

As shown in FIG. 23, the data within memory location 1708 next are readfrom memory location 1708 to LS memory location 1750. FIG. 24 shows thefinal state. A copy of the data in memory location 1708 is stored in LSmemory location 1750. F/E bit 1712 is set to 0 to indicate that the datain memory location 1708 are invalid. This invalidity is the result ofalterations to these data to be made by SPU 1740. The busy bit in memorysegment 1752 also is set to 0. This setting indicates that LS memorylocation 1750 now is available to SPU 1740 for any purpose, i.e., thisLS memory location no longer is in a reserved state waiting for thereceipt of specific data. LS memory location 1750, therefore, now can beaccessed by SPU 1740 for any purpose.

FIGS. 25-31 illustrate the synchronized reading of data from a memorylocation of DRAM 1702, e.g., memory location 1708, to an LS memorylocation of an SPU's local storage, e.g., LS memory location 1752 oflocal storage 1744, when the F/E bit for the memory location of DRAM1702 is set to 0 to indicate that the data in this memory location arenot current or valid. As shown in FIG. 25, to initiate this transfer,the busy bit in memory segment 1752 of LS memory location 1750 is set to1 to reserve this LS memory location for this transfer of data. As shownin FIG. 26, control logic 1742 next issues a synchronize read commandfor memory location 1708 of DRAM 1702. Since the F/E bit associated withthis memory location, F/E bit 1712, is set to 0, the data stored inmemory location 1708 are invalid. As a result, a signal is transmittedto control logic 1742 to block the immediate reading of data from thismemory location.

As shown in FIG. 27, the SPU ID 1714 and LS address 1716 for this readcommand next are written into memory segment 1762. In this case, the SPUID for SPU 1740 and the LS memory location for LS memory location 1750are written into memory segment 1762. When the data within memorylocation 1708 become current, therefore, this SPU ID and LS memorylocation are used for determining the location to which the current dataare to be transmitted.

The data in memory location 1708 become valid and current when an SPUwrites data into this memory location. The synchronized writing of datainto memory location 1708 from, e.g., memory location 1732 of SPU 1722,is illustrated in FIG. 28. This synchronized writing of these data ispermitted because F/E bit 1712 for this memory location is set to 0.

As shown in FIG. 29, following this writing, the data in memory location1708 become current and valid. SPU ID 1714 and LS address 1716 frommemory segment 1762, therefore, immediately are read from memory segment1762, and this information then is deleted from this segment. F/E bit1712 also is set to 0 in anticipation of the immediate reading of thedata in memory location 1708. As shown in FIG. 30, upon reading SPU ID1714 and LS address 1716, this information immediately is used forreading the valid data in memory location 1708 to LS memory location1750 of SPU 1740. The final state is shown in FIG. 31. This figure showsthe valid data from memory location 1708 copied to memory location 1750,the busy bit in memory segment 1752 set to 0 and F/E bit 1712 in memorysegment 1762 set to 0. The setting of this busy bit to 0 enables LSmemory location 1750 now to be accessed by SPU 1740 for any purpose. Thesetting of this F/E bit to 0 indicates that the data in memory location1708 no longer are current and valid.

FIG. 32 summarizes the operations described above and the various statesof a memory location of the DRAM based upon the states of the F/E bit,the SPU ID and the LS address stored in the memory segment correspondingto the memory location. The memory location can have three states. Thesethree states are an empty state 3280 in which the F/E bit is set to 0and no information is provided for the SPU ID or the LS address, a fullstate 3282 in which the F/E bit is set to 1 and no information isprovided for the SPU ID or LS address and a blocking state 3284 in whichthe F/E bit is set to 0 and information is provided for the SPU ID andLS address.

As shown in this figure, in empty state 3280, a synchronized writingoperation is permitted and results in a transition to full state 3282. Asynchronized reading operation, however, results in a transition to theblocking state 3284 because the data in the memory location, when thememory location is in the empty state, are not current.

In full state 3282, a synchronized reading operation is permitted andresults in a transition to empty state 3280. On the other hand, asynchronized writing operation in full state 3282 is prohibited toprevent overwriting of valid data. If such a writing operation isattempted in this state, no state change occurs and an error message istransmitted to the SPU's corresponding control logic.

In blocking state 3284, the synchronized writing of data into the memorylocation is permitted and results in a transition to empty state 3280.On the other hand, a synchronized reading operation in blocking state3284 is prohibited to prevent a conflict with the earlier synchronizedreading operation which resulted in this state. If a synchronizedreading operation is attempted in blocking state 3284, no state changeoccurs and an error message is transmitted to the SPU's correspondingcontrol logic.

The scheme described above for the synchronized reading and writing ofdata from and to the shared DRAM also can be used for eliminating thecomputational resources normally dedicated by a processor for readingdata from, and writing data to, external devices. This input/output(I/O) function could be performed by a PU. However, using a modificationof this synchronization scheme, an SPU running an appropriate programcan perform this function. For example, using this scheme, a PUreceiving an interrupt request for the transmission of data from an I/Ointerface initiated by an external device can delegate the handling ofthis request to this SPU. The SPU then issues a synchronize writecommand to the I/O interface. This interface in turn signals theexternal device that data now can be written into the DRAM. The SPU nextissues a synchronize read command to the DRAM to set the DRAM's relevantmemory space into a blocking state. The SPU also sets to 1 the busy bitsfor the memory locations of the SPU's local storage needed to receivethe data. In the blocking state, the additional memory segmentsassociated with the DRAM's relevant memory space contain the SPU's IDand the address of the relevant memory locations of the SPU's localstorage. The external device next issues a synchronize write command towrite the data directly to the DRAM's relevant memory space. Since thismemory space is in the blocking state, the data are immediately read outof this space into the memory locations of the SPU's local storageidentified in the additional memory segments. The busy bits for thesememory locations then are set to 0. When the external device completeswriting of the data, the SPU issues a signal to the PU that thetransmission is complete.

Using this scheme, therefore, data transfers from external devices canbe processed with minimal computational load on the PU. The SPUdelegated this function, however, should be able to issue an interruptrequest to the PU, and the external device should have direct access tothe DRAM.

The DRAM of each PU includes a plurality of “sandboxes.” A sandboxdefines an area of the shared DRAM beyond which a particular SPU, or setof SPUs, cannot read or write data. These sandboxes provide securityagainst the corruption of data being processed by one SPU by data beingprocessed by another SPU. These sandboxes also permit the downloading ofsoftware cells from network 104 into a particular sandbox without thepossibility of the software cell corrupting data throughout the DRAM. Inthe present invention, the sandboxes are implemented in the hardware ofthe DRAMs and DMACs. By implementing these sandboxes in this hardwarerather than in software, advantages in speed and security are obtained.

The PU of a PU controls the sandboxes assigned to the SPUs. Since the PUnormally operates only trusted programs, such as an operating system,this scheme does not jeopardize security. In accordance with thisscheme, the PU builds and maintains a key control table. This keycontrol table is illustrated in FIG. 33. As shown in this figure, eachentry in key control table 3302 contains an identification (ID) 3304 foran SPU, an SPU key 3306 for that SPU and a key mask 3308. The use ofthis key mask is explained below. Key control table 3302 preferably isstored in a relatively fast memory, such as a static random accessmemory (SRAM), and is associated with the DMAC. The entries in keycontrol table 3302 are controlled by the PU. When an SPU requests thewriting of data to, or the reading of data from, a particular storagelocation of the DRAM, the DMAC evaluates the SPU key 3306 assigned tothat SPU in key control table 3302 against a memory access keyassociated with that storage location.

As shown in FIG. 34, a dedicated memory segment 3410 is assigned to eachaddressable storage location 3406 of a DRAM 3402. A memory access key3412 for the storage location is stored in this dedicated memorysegment. As discussed above, a further additional dedicated memorysegment 3408, also associated with each addressable storage location3406, stores synchronization information for writing data to, andreading data from, the storage-location.

In operation, an SPU issues a DMA command to the DMAC. This commandincludes the address of a storage location 3406 of DRAM 3402. Beforeexecuting this command, the DMAC looks up the requesting SPU's key 3306in key control table 3302 using the SPU's ID 3304. The DMAC thencompares the SPU key 3306 of the requesting SPU to the memory access key3412 stored in the dedicated memory segment 3410 associated with thestorage location of the DRAM to which the SPU seeks access. If the twokeys do not match, the DMA command is not executed. On the other hand,if the two keys match, the DMA command proceeds and the requested memoryaccess is executed.

An alternative embodiment is illustrated in FIG. 35. In this embodiment,the PU also maintains a memory access control table 3502. Memory accesscontrol table 3502 contains an entry for each sandbox within the DRAM.In the particular example of FIG. 35, the DRAM contains 64 sandboxes.Each entry in memory access control table 3502 contains anidentification (ID) 3504 for a sandbox, a base memory address 3506, asandbox size 3508, a memory access key 3510 and an access key mask 3512.Base memory address 3506 provides the address in the DRAM which starts aparticular memory sandbox. Sandbox size 3508 provides the size of thesandbox and, therefore, the endpoint of the particular sandbox.

FIG. 36 is a flow diagram of the steps for executing a DMA command usingkey control table 3302 and memory access control table 3502. In step3602, an SPU issues a DMA command to the DMAC for access to a particularmemory location or locations within a sandbox. This command includes asandbox ID 3504 identifying the particular sandbox for which access isrequested. In step 3604, the DMAC looks up the requesting SPU's key 3306in key control table 3302 using the SPU's ID 3304. In step 3606, theDMAC uses the sandbox ID 3504 in the command to look up in memory accesscontrol table 3502 the memory access key 3510 associated with thatsandbox. In step 3608, the DMAC compares the SPU key 3306 assigned tothe requesting SPU to the access key 3510 associated with the sandbox.In step 3610, a determination is made of whether the two keys match. Ifthe two keys do not match, the process moves to step 3612 where the DMAcommand does not proceed and an error message is sent to either therequesting SPU, the PU or both. On the other hand, if at step 3610 thetwo keys are found to match, the process proceeds to step 3614 where theDMAC executes the DMA command.

The key masks for the SPU keys and the memory access keys providegreater flexibility to this system. A key mask for a key converts amasked bit into a wildcard. For example, if the key mask 3308 associatedwith an SPU key 3306 has its last two bits set to “mask,” designated by,e.g., setting these bits in key mask 3308 to 1, the SPU key can beeither a 1 or a 0 and still match the memory access key. For example,the SPU key might be 1010. This SPU key normally allows access only to asandbox having an access key of 1010. If the SPU key mask for this SPUkey is set to 0001, however, then this SPU key can be used to gainaccess to sandboxes having an access key of either 1010 or 1011.Similarly, an access key 1010 with a mask set to 0001 can be accessed byan SPU with an SPU key of either 1010 or 1011. Since both the SPU keymask and the memory key mask can be used simultaneously, numerousvariations of accessibility by the SPUs to the sandboxes can beestablished.

The present invention also provides a new programming model for theprocessors of system 101. This programming model employs software cells102. These cells can be transmitted to any processor on network 104 forprocessing. This new programming model also utilizes the unique modulararchitecture of system 101 and the processors of system 101.

Software cells are processed directly by the SPUs from the SPU's localstorage. The SPUs do not directly operate on any data or programs in theDRAM. Data and programs in the DRAM are read into the SPU's localstorage before the SPU processes these data and programs. The SPU'slocal storage, therefore, includes a program counter, stack and othersoftware elements for executing these programs. The PU controls the SPUsby issuing direct memory access (DMA) commands to the DMAC.

The structure of software cells 102 is illustrated in FIG. 37. As shownin this figure, a software cell, e.g., software cell 3702, containsrouting information section 3704 and body 3706. The informationcontained in routing information section 3704 is dependent upon theprotocol of network 104. Routing information section 3704 containsheader 3708, destination ID 3710, source ID 3712 and reply ID 3714. Thedestination ID includes a network address. Under the TCP/IP protocol,e.g., the network address is an Internet protocol (IP) address.Destination ID 3710 further includes the identity of the PU and SPU towhich the cell should be transmitted for processing. Source ID 3712contains a network address and identifies the PU and SPU from which thecell originated to enable the destination PU and SPU to obtainadditional information regarding the cell if necessary. Reply ID 3714contains a network address and identifies the PU and SPU to whichqueries regarding the cell, and the result of processing of the cell,should be directed.

Cell body 3706 contains information independent of the network'sprotocol. The exploded portion of FIG. 37 shows the details of cell body3706. Header 3720 of cell body 3706 identifies the start of the cellbody. Cell interface 3722 contains information necessary for the cell'sutilization. This information includes global unique ID 3724, requiredSPUs 3726, sandbox size 3728 and previous cell ID 3730.

Global unique ID 3724 uniquely identifies software cell 3702 throughoutnetwork 104. Global unique ID 3724 is generated on the basis of sourceID 3712, e.g. the unique identification of a PU or SPU within source ID3712, and the time and date of generation or transmission of softwarecell 3702. Required SPUs 3726 provides the minimum number of SPUsrequired to execute the cell. Sandbox size 3728 provides the amount ofprotected memory in the required SPUs' associated DRAM necessary toexecute the cell. Previous cell ID 3730 provides the identity of aprevious cell in a group of cells requiring sequential execution, e.g.,streaming data.

Implementation section 3732 contains the cell's core information. Thisinformation includes DMA command list 3734, programs 3736 and data 3738.Programs 3736 contain the programs to be run by the SPUs (called“spulets”), e.g., SPU programs 3760 and 3762, and data 3738 contain thedata to be processed with these programs. DMA command list 3734 containsa series of DMA commands needed to start the programs. These DMAcommands include DMA commands 3740, 3750, 3755 and 3758. The PU issuesthese DMA commands to the DMAC.

DMA command 3740 includes VID 3742. VID 3742 is the virtual ID of an SPUwhich is mapped to a physical ID when the DMA commands are issued. DMAcommand 3740 also includes load command 3744 and address 3746. Loadcommand 3744 directs the SPU to read particular information from theDRAM into local storage. Address 3746 provides the virtual address inthe DRAM containing this information. The information can be, e.g.,programs from programs section 3736, data from data section 3738 orother data. Finally, DMA command 3740 includes local storage address3748. This address identifies the address in local storage where theinformation should be loaded. DMA commands 3750 contain similarinformation. Other DMA commands are also possible.

DMA command list 3734 also includes a series of kick commands, e.g.,kick commands 3755 and 3758. Kick commands are commands issued by a PUto an SPU to initiate the processing of a cell. DMA kick command 3755includes virtual SPU ID 3752, kick command 3754 and program counter3756. Virtual SPU ID 3752 identifies the SPU to be kicked, kick command3754 provides the relevant kick command and program counter 3756provides the address for the program counter for executing the program.DMA kick command 3758 provides similar information for the same SPU oranother SPU.

As noted, the PUs treat the SPUs as independent processors, notco-processors. To control processing by the SPUs, therefore, the PU usescommands analogous to remote procedure calls. These commands aredesignated “SPU Remote Procedure Calls” (SRPCs). A PU implements an SRPCby issuing a series of DMA commands to the DMAC. The DMAC loads the SPUprogram and its associated stack frame into the local storage of an SPU.The PU then issues an initial kick to the SPU to execute the SPUProgram.

FIG. 38 illustrates the steps of an SRPC for executing an spulet. Thesteps performed by the PU in initiating processing of the spulet by adesignated SPU are shown in the first portion 3802 of FIG. 38, and thesteps performed by the designated SPU in processing the spulet are shownin the second portion 3804 of FIG. 38.

In step 3810, the PU evaluates the spulet and then designates an SPU forprocessing the spulet. In step 3812, the PU allocates space in the DRAMfor executing the spulet by issuing a DMA command to the DMAC to setmemory access keys for the necessary sandbox or sandboxes. In step 3814,the PU enables an interrupt request for the designated SPU to signalcompletion of the spulet. In step 3818, the PU issues a DMA command tothe DMAC to load the spulet from the DRAM to the local storage of theSPU. In step 3820, the DMA command is executed, and the spulet is readfrom the DRAM to the SPU's local storage. In step 3822, the PU issues aDMA command to the DMAC to load the stack frame associated with thespulet from the DRAM to the SPU's local storage. In step 3823, the DMAcommand is executed, and the stack frame is read from the DRAM to theSPU's local storage. In step 3824, the PU issues a DMA command for theDMAC to assign a key to the SPU to allow the SPU to read and write datafrom and to the hardware sandbox or sandboxes designated in step 3812.In step 3826, the DMAC updates the key control table (KTAB) with the keyassigned to the SPU. In step 3828, the PU issues a DMA command “kick” tothe SPU to start processing of the program. Other DMA commands may beissued by the PU in the execution of a particular SRPC depending uponthe particular spulet.

As indicated above, second portion 3804 of FIG. 38 illustrates the stepsperformed by the SPU in executing the spulet. In step 3830, the SPUbegins to execute the spulet in response to the kick command issued atstep 3828. In step 3832, the SPU, at the direction of the spulet,evaluates the spulet's associated stack frame. In step 3834, the SPUissues multiple DMA commands to the DMAC to load data designated asneeded by the stack frame from the DRAM to the SPU's local storage. Instep 3836, these DMA commands are executed, and the data are read fromthe DRAM to the SPU's local storage. In step 3838, the SPU executes thespulet and generates a result. In step 3840, the SPU issues a DMAcommand to the DMAC to store the result in the DRAM. In step 3842, theDMA command is executed and the result of the spulet is written from theSPU's local storage to the DRAM. In step 3844, the SPU issues aninterrupt request to the PU to signal that the SRPC has been completed.

The ability of SPUs to perform tasks independently under the directionof a PU enables a PU to dedicate a group of SPUs, and the memoryresources associated with a group of SPUs, to performing extended tasks.For example, a PU can dedicate one or more SPUs, and a group of memorysandboxes associated with these one or more SPUs, to receiving datatransmitted over network 104 over an extended period and to directingthe data received during this period to one or more other SPUs and theirassociated memory sandboxes for further processing. This ability isparticularly advantageous to processing streaming data transmitted overnetwork 104, e.g., streaming MPEG or streaming ATRAC audio or videodata. A PU can dedicate one or more SPUs and their associated memorysandboxes to receiving these data and one or more other SPUs and theirassociated memory sandboxes to decompressing and further processingthese data. In other words, the PU can establish a dedicated pipelinerelationship among a group of SPUs and their associated memory sandboxesfor processing such data.

In order for such processing to be performed efficiently, however, thepipeline's dedicated SPUs and memory sandboxes should remain dedicatedto the pipeline during periods in which processing of spulets comprisingthe data stream does not occur. In other words, the dedicated SPUs andtheir associated sandboxes should be placed in a reserved state duringthese periods. The reservation of an SPU and its associated memorysandbox or sandboxes upon completion of processing of an spulet iscalled a “resident termination.” A resident termination occurs inresponse to an instruction from a PU.

FIGS. 39, 40A and 40B illustrate the establishment of a dedicatedpipeline structure comprising a group of SPUs and their associatedsandboxes for the processing of streaming data, e.g., streaming MPEGdata. As shown in FIG. 39, the components of this pipeline structureinclude PE 3902 and DRAM 3918. PE 3902 includes PU 3904, DMAC 3906 and aplurality of SPUs, including SPU 3908, SPU 3910 and SPU 3912.Communications among PU 3904, DMAC 3906 and these SPUs occur through PEbus 3914. Wide bandwidth bus 3916 connects DMAC 3906 to DRAM 3918. DRAM3918 includes a plurality of sandboxes, e.g., sandbox 3920, sandbox3922, sandbox 3924 and sandbox 3926.

FIG. 40A illustrates the steps for establishing the dedicated pipeline.In step 4010, PU 3904 assigns SPU 3908 to process a network spulet. Anetwork spulet comprises a program for processing the network protocolof network 104. In this case, this protocol is the Transmission ControlProtocol/Internet Protocol (TCP/IP). TCP/IP data packets conforming tothis protocol are transmitted over network 104. Upon receipt, SPU 3908processes these packets and assembles the data in the packets intosoftware cells 102. In step 4012, PU 3904 instructs SPU 3908 to performresident terminations upon the completion of the processing of thenetwork spulet. In step 4014, PU 3904 assigns PUs 3910 and 3912 toprocess MPEG spulets. In step 4015, PU 3904 instructs SPUs 3910 and 3912also to perform resident terminations upon the completion of theprocessing of the MPEG spulets. In step 4016, PU 3904 designates sandbox3920 as a source sandbox for access by SPU 3908 and SPU 3910. In step4018, PU 3904 designates sandbox 3922 as a destination sandbox foraccess by SPU 3910. In step 4020, PU 3904 designates sandbox 3924 as asource sandbox for access by SPU 3908 and SPU 3912. In step 4022, PU3904 designates sandbox 3926 as a destination sandbox for access by SPU3912. In step 4024, SPU 3910 and SPU 3912 send synchronize read commandsto blocks of memory within, respectively, source sandbox 3920 and sourcesandbox 3924 to set these blocks of memory into the blocking state. Theprocess finally moves to step 4028 where establishment of the dedicatedpipeline is complete and the resources dedicated to the pipeline arereserved. SPUs 3908, 3910 and 3912 and their associated sandboxes 3920,3922, 3924 and 3926, therefore, enter the reserved state.

FIG. 40B illustrates the steps for processing streaming MPEG data bythis dedicated pipeline. In step 4030, SPU 3908, which processes thenetwork spulet, receives in its local storage TCP/IP data packets fromnetwork 104. In step 4032, SPU 3908 processes these TCP/IP data packetsand assembles the data within these packets into software cells 102. Instep 4034, SPU 3908 examines header 3720 (FIG. 37) of the software cellsto determine whether the cells contain MPEG data. If a cell does notcontain MPEG data, then, in step 4036, SPU 3908 transmits the cell to ageneral purpose sandbox designated within DRAM 3918 for processing otherdata by other SPUs not included within the dedicated pipeline. SPU 3908also notifies PU 3904 of this transmission.

On the other hand, if a software cell contains MPEG data, then, in step4038, SPU 3908 examines previous cell ID 3730 (FIG. 37) of the cell toidentify the MPEG data stream to which the cell belongs. In step 4040,SPU 3908 chooses an SPU of the dedicated pipeline for processing of thecell. In this case, SPU 3908 chooses SPU 3910 to process these data.This choice is based upon previous cell ID 3730 and load balancingfactors. For example, if previous cell ID 3730 indicates that theprevious software cell of the MPEG data stream to which the softwarecell belongs was sent to SPU 3910 for processing, then the presentsoftware cell normally also will be sent to SPU 3910 for processing. Instep 4042, SPU 3908 issues a synchronize write command to write the MPEGdata to sandbox 3920. Since this sandbox previously was set to theblocking state, the MPEG data, in step 4044, automatically is read fromsandbox 3920 to the local storage of SPU 3910. In step 4046, SPU 3910processes the MPEG data in its local storage to generate video data. Instep 4048, SPU 3910 writes the video data to sandbox 3922. In step 4050,SPU 3910 issues a synchronize read command to sandbox 3920 to preparethis sandbox to receive additional MPEG data. In step 4052, SPU 3910processes a resident termination. This processing causes this SPU toenter the reserved state during which the SPU waits to processadditional MPEG data in the MPEG data stream.

Other dedicated structures can be established among a group of SPUs andtheir associated sandboxes for processing other types of data. Forexample, as shown in FIG. 41, a dedicated group of SPUs, e.g., SPUs4102, 4108 and 4114, can be established for performing geometrictransformations upon three dimensional objects to generate twodimensional display lists. These two dimensional display lists can befurther processed (rendered) by other SPUs to generate pixel data. Toperform this processing, sandboxes are dedicated to SPUs 4102, 4108 and4114 for storing the three dimensional objects and the display listsresulting from the processing of these objects. For example, sourcesandboxes 4104, 4110 and 4116 are dedicated to storing the threedimensional objects processed by, respectively, SPU 4102, SPU 4108 andSPU 4114. In a similar manner, destination sandboxes 4106, 4112 and 4118are dedicated to storing the display lists resulting from the processingof these three dimensional objects by, respectively, SPU 4102, SPU 4108and SPU 4114.

Coordinating SPU 4120 is dedicated to receiving in its local storage thedisplay lists from destination sandboxes 4106, 4112 and 4118. SPU 4120arbitrates among these display lists and sends them to other SPUs forthe rendering of pixel data.

The processors of system 101 also employ an absolute timer. The absolutetimer provides a clock signal to the SPUs and other elements of a PUwhich is both independent of, and faster than, the clock signal drivingthese elements. The use of this absolute timer is illustrated in FIG.42.

As shown in this figure, the absolute timer establishes a time budgetfor the performance of tasks by the SPUs. This time budget provides atime for completing these tasks which is longer than that necessary forthe SPUs' processing of the tasks. As a result, for each task, there is,within the time budget, a busy period and a standby period. All spuletsare written for processing on the basis of this time budget regardlessof the SPUs' actual processing time or speed.

For example, for a particular SPU of a PU, a particular task may beperformed during busy period 4202 of time budget 4204. Since busy period4202 is less than time budget 4204, a standby period 4206 occurs duringthe time budget. During this standby period, the SPU goes into a sleepmode during which less power is consumed by the SPU.

The results of processing a task are not expected by other SPUs, orother elements of a PU, until a time budget 4204 expires. Using the timebudget established by the absolute timer, therefore, the results of theSPUs' processing always are coordinated regardless of the SPUs' actualprocessing speeds.

In the future, the speed of processing by the SPUs will become faster.The time budget established by the absolute timer, however, will remainthe same. For example, as shown in FIG. 42, an SPU in the future willexecute a task in a shorter period and, therefore, will have a longerstandby period. Busy period 4208, therefore, is shorter than busy period4202, and standby period 4210 is longer than standby period 4206.However, since programs are written for processing on the basis of thesame time budget established by the absolute timer, coordination of theresults of processing among the SPUs is maintained. As a result, fasterSPUs can process programs written for slower SPUs without causingconflicts in the times at which the results of this processing areexpected.

In lieu of an absolute timer to establish coordination among the SPUs,the PU, or one or more designated SPUs, can analyze the particularinstructions or microcode being executed by an SPU in processing anspulet for problems in the coordination of the SPUs' parallel processingcreated by enhanced or different operating speeds. “No operation”(“NOOP”) instructions can be inserted into the instructions and executedby some of the SPUs to maintain the proper sequential completion ofprocessing by the SPUs expected by the spulet. By inserting these NOOPsinto the instructions, the correct timing for the SPUs' execution of allinstructions can be maintained.

FIG. 43 is a diagram showing a processor element architecture whichincludes a plurality of heterogeneous processors. The heterogeneousprocessors share a common memory and a common bus. Processor elementarchitecture (PEA) 4300 sends and receives information to/from externaldevices through input output 4370, and distributes the information tocontrol plane 4310 and data plane 4340 using processor element bus 4360.Control plane 4310 manages PEA 4300 and distributes work to data plane4340.

Control plane 4310 includes processing unit 4320 which runs operatingsystem (OS) 4325. For example, processing unit 4320 may be a Power PCcore that is embedded in PEA 4300 and OS 4325 may be a Linux operatingsystem. Processing unit 4320 manages a common memory map table for PEA4300. The memory map table corresponds to memory locations included inPEA 4300, such as L2 memory 4330 as well as non-private memory includedin data plane 4340 (see FIGS. 44A, 44B, and corresponding text forfurther details regarding memory mapping).

Data plane 4340 includes Synergistic Processing Complex's (SPC) 4345,4350, and 4355. Each SPC is used to process data information and eachSPC may have different instruction sets. For example, PEA 4300 may beused in a wireless communications system and each SPC may be responsiblefor separate processing tasks, such as modulation, chip rate processing,encoding, and network interfacing. In another example, each SPC may haveidentical instruction sets and may be used in parallel to performoperations benefiting from parallel processes. Each SPC includes asynergistic processing unit (SPU) which is a processing core, such as adigital signal processor, a microcontroller, a microprocessor, or acombination of these cores.

SPC 4345, 4350, and 4355 are connected to processor element bus 4360which passes information between control plane 4310, data plane 4340,and input/output 4370. Bus 4360 is an on-chip coherent multi-processorbus that passes information between I/O 4370, control plane 4310, anddata plane 4340. Input/output 4370 includes flexible input-output logicwhich dynamically assigns interface pins to input output controllersbased upon peripheral devices that are connected to PEA 4300. Forexample, PEA 4300 may be connected to two peripheral devices, such asperipheral A and peripheral B, whereby each peripheral connects to aparticular number of input and output pins on PEA 4300. In this example,the flexible input-output logic is configured to route PEA 4300'sexternal input and output pins that are connected to peripheral A to afirst input output controller (i.e. IOC A) and route PEA 4300's externalinput and output pins that are connected to peripheral B to a secondinput output controller (i.e. IOC B) (see FIGS. 47A, 47B, 48,49, 50, andcorresponding text for further details regarding dynamic pinassignments).

FIG. 44A is a diagram showing a device that uses a common memory map toshare memory between heterogeneous processors. Device 4400 includesprocessing unit 4430 which executes an operating system for device 4400.Processing unit 4430 is similar to processing unit 4320 shown in FIG.43. Processing unit 4430 uses system memory map 4420 to allocate memoryspace throughout device 4400. For example, processing unit 4430 usessystem memory map 4420 to identify and allocate memory areas whenprocessing unit 4430 receives a memory request. Processing unit 4430access L2 memory 4425 for retrieving application and data information.L2 memory 4425 is similar to L2 memory 4330 shown in FIG. 43.

System memory map 4420 separates memory mapping areas into regions whichare regions 4435, 4445, 4450, 4455, and 4460. Region 4435 is a mappingregion for external system memory which may be controlled by a separateinput output device. Region 4445 is a mapping region for non-privatestorage locations corresponding to one or more synergistic processingcomplexes, such as SPC 4402. SPC 4402 is similar to the SPC's shown inFIG. 43, such as SPC A 4345. SPC 4402 includes local memory, such aslocal store 4410, whereby portions of the local memory may be allocatedto the overall system memory for other processors to access. Forexample, 1 MB of local store 4410 may be allocated to non-privatestorage whereby it becomes accessible by other heterogeneous processors.In this example, local storage aliases 4445 manages the 1 MB ofnonprivate storage located in local store 4410.

Region 4450 is a mapping region for translation lookaside buffer's(TLB's) and memory flow control (MFC registers. A translation lookasidebuffer includes cross-references between virtual address and realaddresses of recently referenced pages of memory. The memory flowcontrol provides interface functions between the processor and the bussuch as DMA control and synchronization.

Region 4455 is a mapping region for the operating system and is pinnedsystem memory with bandwidth and latency guarantees. Region 4460 is amapping region for input output devices that are external to device 4400and are defined by system and input output architectures.

Synergistic processing complex (SPC) 4402 includes synergisticprocessing unit (SPU) 4405, local store 4410, and memory management unit(MMU) 4415. Processing unit 4430 manages SPU 4405 and processes data inresponse to processing unit 4430's direction. For example SPU 4405 maybe a digital signaling processing core, a microprocessor core, a microcontroller core, or a combination of these cores. Local store 4410 is astorage area that SPU 4405 configures for a private storage area and anon-private storage area. For example, if SPU 4405 requires asubstantial amount of local memory, SPU 4405 may allocate 100% of localstore 4410 to private memory. In another example, if SPU 4405 requires aminimal amount of local memory, SPU 4405 may allocate 10% of local store4410 to private memory and allocate the remaining 90% of local store4410 to non-private memory (see FIG. 44B and corresponding text forfurther details regarding local store configuration).

The portions of local store 4410 that are allocated to non-privatememory are managed by system memory map 4420 in region 4445. Thesenon-private memory regions may be accessed by other SPU's or byprocessing unit 4430. MMU 4415 includes a direct memory access (DMA)function and passes information from local store 4410 to other memorylocations within device 4400.

FIG. 44B is a diagram showing a local storage area divided into privatememory and non-private memory. During system boot, synergisticprocessing unit (SPU) 4460 partitions local store 4470 into two regionswhich are private store 4475 and non-private store 4480. SPU 4460 issimilar to SPU 4405 and local store 4470 is similar to local store 4410that are shown in FIG. 44A. Private store 4475 is accessible by SPU 4460whereas non-private store 4480 is accessible by SPU 4460 as well asother processing units within a particular device. SPU 4460 uses privatestore 4475 for fast access to data. For example, SPU 4460 may beresponsible for complex computations that require SPU 4460 to quicklyaccess extensive amounts of data that is stored in memory. In thisexample, SPU 4460 may allocate 100% of local store 4470 to private store4475 in order to ensure that SPU 4460 has enough local memory to access.In another example, SPU 4460 may not require a large amount of localmemory and therefore, may allocate 10% of local store 4470 to privatestore 4475 and allocate the remaining 90% of local store 4470 tonon-private store 4480.

A system memory mapping region, such as local storage aliases 4490,manages portions of local store 4470 that are allocated to non-privatestorage. Local storage aliases 4490 is similar to local storage aliases4445 that is shown in FIG. 44A. Local storage aliases 4490 managesnon-private storage for each SPU and allows other SPU's to access thenon-private storage as well as a device's control processing unit.

FIG. 45 is a flowchart showing steps taken in configuring local memorylocated in a synergistic processing complex (SPC). An SPC includes asynergistic processing unit (SPU) and local memory. The SPU partitionsthe local memory into a private storage region and a nonprivate storageregion. The private storage region is accessible by the correspondingSPU whereas the non-private storage region is accessible by other SPU'sand the device's central processing unit. The non-private storage regionis managed by the device's system memory map in which the device'scentral processing unit controls.

SPU processing commences at 4500, whereupon processing selects a firstSPC at step 4510. Processing receives a private storage region size fromprocessing unit 4530 at step 4520. Processing unit 4530 is a mainprocessor that runs an operating system which manages private andnon-private memory allocation. Processing unit 4530 is similar toprocessing units 4320 and 4430 shown in FIGS. 43 and 44, respectively.Processing partitions local store 4550 into private and non-privateregions at step 4540. Once the local storage area is configured,processing informs processing unit 4530 to configure memory map 4565 tomanage local store 4550's non-private storage region (step 4560). Memorymap 4565 is similar to memory map 4420 that is shown in FIG. 44A andincludes local storage aliases which manage each SPC's allocatednon-private storage area (see FIGS. 44A, 44B, 45, and corresponding textfor further details regarding local storage aliases).

A determination is made as to whether the device includes more SPC's toconfigure (decision 4570). For example, the device may include fiveSPC's, each of which is responsible for different tasks and each ofwhich require different sizes of corresponding private storage. If thedevice has more SPC's to configure, decision 4570 branches to “Yes”branch 4572 whereupon processing selects (step 4580) and processes thenext SPC's memory configuration. This looping continues until the deviceis finished processing each SPC, at which point decision 4570 branchesto “No” branch 4578 whereupon processing ends at 4590.

FIG. 46A is a diagram showing a central device with predefinedinterfaces, such as device Z 4600, connected to two peripheral devices,such as device A 4635 and device B 4650. Device Z 4600 is designed suchthat its external interface pins are designated to connect toperipherals with particular interfaces. For example, device Z 4600 maybe a microprocessor and device A 4635 may be an external memorymanagement device and device B 4650 may be a network interface device.In the example shown in FIG. 46A, device Z 4600 provides three inputpins and four output pins to the external memory management device anddevice Z 4600 provides two input pins and three output pins to thenetwork interface device.

Device Z 4600 includes input output controller (IOC) A 4605 and IOC B4620. Each IOC manages data exchange for a particular peripheral devicethrough designated interfaces on device Z 4600. Interfaces 4610 and 4615are committed to IOC A 4605 while interfaces 4625 and 4630 are committedto IOC B 4620. In order to maximize device Z 4600's pin utilization,peripheral devices connected to device Z 4600 are required to havematching interfaces (e.g. device A 4635 and device B 4650).

Device A 4635 includes interfaces 4640 and 4645. Interface 4640 includesthree output pins which match the three input pins included in device Z4600's interface 4610. In addition, interface 4645 includes four inputpins which match the four output pins included in device Z 4600'sinterface 4615. When connected, device A 4635 utilizes each pin includedin device Z 4600's interfaces 4610 and 4615.

Device B 4650 includes interfaces 4655 and 4660. Interface 4655 includestwo output pins which match the two input pins included in device Z4600's interface 4625. In addition, interface 4660 includes three inputpins which match the three output pins included in device Z 4600'sinterface 4630: When connected, device B 4650 utilizes each pin includedin device Z 4600's interfaces 4625 and 4630. A challenge found, however,is that device Z 4600's pin utilization is not maximized when peripheraldevices are connected to device Z 4600 that do not conform to device Z4600's pre-defined interfaces (see FIG. 46B and corresponding text forfurther details regarding other peripheral device connections).

FIG. 46B is a diagram showing two peripheral devices connected to acentral device with mismatching input and output interfaces. Device Z4600 includes pre-defined interfaces 4610 and 4615 which correspond toinput output controller (IOC) A 4605. Device Z 4600 also includesinterfaces 4625 and 4630 which correspond to IOC B 4620 (see FIG. 46Aand corresponding text for further details regarding pre-defined pinassignments).

Device C 4670 is a peripheral device which includes interfaces 4675 and4680. Interface 4675 connects to device Z 4600's interface 4610 whichallows device C 4670 to send data to device Z 4600. Interface 4675includes four output pins whereas interface 4610 includes three inputpins. Since interface 4675 has more pins than interface 4610 and sinceinterface 4610 is pre-defined, interface 4675's pin 4678 does not have acorresponding pin to connect in interface 4610 and, as such, device C4670 is not able to send data to device Z 4600 at its maximum rate.Interface 4680 connects to device Z 4600's interface 4615 which allowsdevice C 4670 to receive data from device Z 4600.

Interface 4680 includes five input pins whereas interface 4615 includesfour output pins. Since interface 4680 has more pins than interface4615, interface 4680's pin 4682 does not have a corresponding pin toconnect in interface 4615 and, as such, device C 4670 is not able toreceive data from device Z 4600 at its maximum rate.

Device D 4685 is a peripheral device which includes interfaces 4690 and4695. Interface 4690 connects to device Z 4600's interface 4625 whichallows device D 4685 to send data to device Z 4600. Interface 4625includes two input pins whereas interface 4690 includes one output pin.Since interface 4625 has more pins than interface 4690, interface 4625'spin 4628 does not have a corresponding pin to connect in interface 4690and, as such, device Z 4600 is not able to receive data from device D4685 at its maximum rate.

Interface 4695 connects to device Z 4600's interface 4630 which allowsdevice D 4685 to receive data from device Z 4600. Interface 4630includes three output pins whereas interface 4695 includes two inputpins. Since interface 4630 has more pins than interface 4695, interface4630's pin 4632 does not have a corresponding pin to connect ininterface 4695 and, as such, device Z 4600 is not able to send data todevice D 4685 at its maximum rate.

Since interfaces 4610, 4615, 4625, and 4630 are pre-defined interfaces,device Z 4600 is not able to use unused pins in one interface tocompensate for needed pins in another interface. The example in FIG. 46Bshows that interface 4610 requires one more input pin and interface 4625is not using one of its input pins (e.g. pin 4628). Since interfaces4610 and 4625 are pre-defined, pin 4628 cannot be used with interface4610 to receive data from device C 4670. In addition, the example inFIG. 46B shows that interface 4615 requires one more output pin andinterface 4630 is not using one of its output pins (e.g. pin 4632).Since interfaces 4615 and 4630 are pre-defined, pin 4632 cannot be usedwith interface 4615 to send data to device C 4670. Due to device Z4600's pre-defined interfaces, IOC A 4605 and IOC B 4620 are not able tomaximize data throughput to either peripheral device that is shown inFIG. 46B.

FIG. 47A is a diagram showing a device with dynamic interfaces that isconnected to a first set of peripheral devices. Device Z 4700 includestwo input output controllers (IOC's) which are IOC A 4705 and IOC B4710. IOC A 4705 and IOC B 4710 are similar to IOC A 4605 and IOC B4620, respectively, that are shown in FIGS. 46A and 46B. IOC A 4705 andIOC B 4710 are responsible for exchanging information between device Z4700 and peripheral devices connected to device Z 4700. Device Z 4700exchanges information between peripheral devices using dynamicinterfaces 4730 and 4735.

Interface 4730 includes five input pins, each of which is dynamicallyassigned to either IOC A 4705 or IOC B 4710 using flexible input-outputA 4720 and flexible input-output B 4725, respectively. Interface 4735includes seven output pins, each of which is dynamically assigned toeither IOC A 4705 or IOC B 4710 using flexible input-output A 4720 andflexible input-output B 4725 respectively. Flexible input-output control4715 configures flexible input-output A 4720 and flexible input-output B4725 at a particular time during device Z 4700's initialization process,such as system boot. Device Z 4700 informs flexible input-output control4715 as to which interface pins are to be assigned to IOC A 4705 andwhich interface pins are to be assigned to IOC B 4710.

With peripheral devices connected to device Z 4700 as shown in FIG. 47A,flexible input-output control 4715 assigns three input pins of interface4730 (e.g. In-1, In-2, In-3) to IOC A 4705 using flexible input-output A4720 in communicate with device A 4740 through to match the three outputpins included in device A 4740's interface 4745. Device A 4740 issimilar to device A 4635 that is shown in FIGS. 46A and 46B. Inaddition, flexible input-output control 4715 assigns the remaining twoinput pins in interface 4730 (e.g. In-4, In-5) to IOC B 4710 usingflexible input-output B 4725 in order to communicate with device B 4755through the two output pins included in device B 4755's interface 4760(see FIG. 50 and corresponding text for further details regardingflexible input-output configuration). Device B 4755 is similar to deviceB 4650 that is shown in FIGS. 46A and 46B. As one skilled in the art canappreciate, a dynamic input interface may include more or less inputpins than what is shown in FIG. 47A.

For output pin assignments, flexible input-output control 4715 assignsfour output pins of interface 4735 (e.g. Out-1 through Out-4) to IOC A4720 using flexible input-output A 4720 in order to communicate withdevice A 4740 through the four input pins included in device A 4740'sinterface 4750. In addition, flexible input-output control 4715 assignsthe remaining three output pins in interface 4735 (e.g. Out-5 throughOut-7) to IOC B 4710 using flexible input-output B 4725 in order tocommunicate with device B 4755 through the three input pins included indevice B 4755's interface 4765 (see FIG. 50 and corresponding text forfurther details regarding flexible input-output configuration). As oneskilled in the art can appreciate, a dynamic output interface mayinclude more or less output pins than what is shown in FIG. 47A.

When a developer connects peripheral devices with different interfacesto device Z 4700, the developer programs flexible input-output control4715 to configure flexible input-output A 4720 and flexible input-outputB 4725 in a manner suitable for the newly connected peripheral devicesinterfaces (see FIG. 47B and corresponding text for further details).

FIG. 47B is a diagram showing a central device with dynamic interfacesthat has re-allocated pin assignments in order to match two newlyconnected peripheral devices, such as device C 4770 and device D 4785.Device Z 4700 was originally configured to interface with peripheraldevices other than device C 4770 and device D 4785 (see FIG. 47A andcorresponding text for further details). Device C 4770 and device D 4785include interfaces different than the previous peripheral devices thatdevice Z 4700 was connected. Device C 4770 and device D 4785 are similarto device C 4670 and device D 4685, respectively, that are shown inFIGS. 46A and 46B.

Upon boot-up or initialization, flexible input-output control 4715re-configures flexible input-output A 4720 and flexible input-output B4725 in a manner that corresponds to device C 4770 and device D 4785interfaces. With peripheral devices connected as shown in FIG. 47B,flexible input-output control 4715 assigns four input pins of interface4730 (e.g. In-1 through In-4) to IOC-A 4705 using flexible input-outputA 4720 in order to communicate with device C 4770 through the fouroutput pins included in device C 4770's interface 4775. In addition,flexible input-output control 4715 assigns the remaining input pin ininterface 4730 (e.g. In-) to IOC B 4710 using flexible input-output B4725 in order to communicate with device D 4785 through the output pinincluded in device D 4785's interface 4790 (see FIG. 50 andcorresponding text for further details regarding flexible input-outputconfiguration). As one skilled in the art can appreciate, a dynamicinput interface may include more or less input pins, as well as more orless interfaces may be used, than what is shown in FIG. 47B.

For output pin assignments, flexible input-output control 4715 assignsfive output pins of interface 4735 (e.g. Out-1 through Out-5) to IOC A4705 using flexible input-output A 4720 in order to communicate withdevice C 4770 through the five input pins included in device C 4770'sinterface 4780. In addition, flexible input-output control 4715 assignsthe remaining two output pins in interface 4735 (e.g. Out-6 and Out-7)to IOC B 4710 using flexible input-output B 4725 in order to communicatewith device D 4785 through the two input pins included in device D4785's interface 4795 (see FIG. 50 and corresponding text for furtherdetails regarding flexible input-output configuration). As one skilledin the art can appreciate, a dynamic input interface may include more orless input pins, as well as more or less interfaces may be used, thanwhat is shown in FIG. 47B.

Flexible input-output control 4715, flexible input-output A 4720, andflexible input-output B 4725 allow device Z 4700 to maximize interfaceutilization by reassigning pins included in interfaces 4730 and 4735based upon peripheral device interfaces that are connected to device Z4700.

FIG. 48 is a flowchart showing steps taken in a device configuring itsdynamic input and output interfaces based upon peripheral devices thatare connected to the device. The device includes flexible input-outputlogic which is configured to route each interface pin to a particularinput output controller (IOC). Each IOC is responsible for exchanginginformation between the device and a particular peripheral device (seeFIGS. 47A, 47B, 50, and corresponding text for further details regardingflexible input-output logic configuration). The example in FIG. 48 showsthat the device is configuring two flexible input-output blocks, such asflexible input-output A 4840 and flexible input-output B 4860. Flexibleinput-output A 4840 and flexible input-output B 4860 are similar toflexible input-output A 4720 and flexible input-output B 4725,respectively, that are shown in FIGS. 47A and 47B. As one skilled in theart can appreciate, more or less flexible input-output blocks may beconfigured using the same technique as shown in FIG. 48.

Processing commences at 4800, whereupon processing receives a number ofinput pins to allocate to flexible input-output A 4840 from processingunit 4820 (step 4810). Processing unit 4820 is similar to processingunits 4320, 4430, and 4530 shown in FIGS. 43, 44, and 45, respectively.Processing assigns the requested number of input pins to flexibleinput-output A 4840 at step 4830 by starting at the lowest numbered pinand assigning pins sequentially until flexible input-output A 4840 isassigned the proper number of pins (see FIGS. 49A, 50, and correspondingtext for further details regarding input pin assignments). Processingassigns remaining input pins to flexible input-output B 4860 at step4850. For example, a device's dynamic interface may include five inputpins that are available for use and flexible input-output A 4840 may beassigned three input pins. In this example, flexible input-output B 4860is assigned the remaining two input pins. As one skilled in the art canappreciate, other pin assignment methods may be used to configureflexible input-output logic.

Processing receives a number of output pins to allocate to flexibleinput-output A 4840 from processing unit 4820 at step 4870. Flexibleinput-output control assigns the requested number of output pins toflexible input-output A 4840 at step 4880 by starting at the lowestnumbered pin and assigning pins sequentially until flexible input-outputA 4840 is assigned the proper number of output pins (see FIG. 7B andcorresponding text for further details regarding output pinassignments). Processing assigns the remaining output pins to flexibleinput-output B 4860 at step 4890. For example, a device may includeseven output pins that are available for use and flexible input-output A4840 may be assigned four output pins. In this example, flexibleinput-output B 4860 is assigned the remaining three output pins. As oneskilled in the art can appreciate, other pin assignment methods may beused to configure flexible input-output logic. Processing ends at 4895.

FIG. 49A is a diagram showing input pin assignments for flexibleinput-output logic corresponding to two input controllers. A device usesflexible input-output logic between the device's physical interface andthe device's input controllers in order to dynamically assign each inputpin to a particular input controller (see FIGS. 47A, 47B, 48, 50, andcorresponding text for further details regarding flexible input-outputlogic location and configuration). Each input controller hascorresponding flexible input-output logic. The example in FIG. 49A showspin assignments for flexible input-output A and flexible input-output Bwhich correspond to an input controller A and an input controller B.

The device has five input pins to assign to either flexible input-outputlogic A or flexible input-output logic B which are pins 4925, 4930,4935, 4940, and 4945. In order to minimize pin assignment complexity,the device assigns input pins to flexible input-output logic A startingwith the first input pin. The example shown in FIG. 49A shows thatflexible input-output logic A input pin assignments start at arrow4910's starting point, and progress in the direction of arrow 4910 untilflexible input-output logic A is assigned the correct number of inputpins. For example, if flexible input-output logic A requires three inputpins, the device starts the pin assignment process by assigning pin 4925to flexible input-output logic A, and proceeds to assign pins 4930 and4935 to flexible input-output logic A.

Once the device is finished assigning pins to flexible input-outputlogic A, the device assigns input pins to flexible input-output logic B.The example shown in FIG. 49A shows that flexible input-output logic Binput pin assignments start at arrow 4920's starting point, and progressin the direction of arrow 4920 until flexible input-output logic B isassigned the correct number of input pins. For example, if flexibleinput-output logic B requires two input pins, the device starts the pinassignment process by assigning pin 4945 to flexible input-output logicB, and then assigns pin 4940 to flexible input-output logic B. As oneskilled in the art can appreciate, other methods of input pin assignmentmethods may be used for allocating input pins to flexible input-outputlogic.

FIG. 49B is a diagram showing output pin assignments for flexibleinput-output logic corresponding to two output controllers. As discussedin FIG. 49A above, a device uses flexible input-output logic between thedevice's physical interface and the device's input controllers in orderto dynamically assign each input pin to a particular input controller.Similarly, the device uses the flexible input-output logic todynamically assign each output pin to a particular output controller.The example in FIG. 49B shows pin assignments for flexible input-outputA and flexible input-output B which correspond to output controller Aand output controller B.

The device has seven output pins to assign to either flexibleinput-output logic A or flexible input-output logic B which are pins4960 through 4990. In order to minimize pin assignment complexity, thedevice assigns output pins to flexible input-output logic A startingwith the first output pin. The example shown in FIG. 49B shows thatflexible input-output logic A output pin assignments start at arrow4955's starting point, and progress in the direction of arrow 4955 untilflexible input-output logic A is assigned the correct number of outputpins. For example, if flexible input-output logic A requires threeoutput pins, the device starts the pin assignment process by assigningpin 4960 to flexible input-output logic A, and proceeds to assign pins4970 and 4975 to flexible input-output logic A.

Once the device is finished assigning output pins to flexibleinput-output logic A, the device assigns output pins to flexibleinput-output logic B. The example shown in FIG. 49B shows that flexibleinput-output logic B output pin assignments start at arrow 4962'sstarting point, and progress in the direction of arrow 4962 untilflexible input-output logic B is assigned the correct number of outputpins. For example, if flexible input-output logic B requires two outputpins, the device starts the pin assignment process by assigning pin 4990to flexible input-output logic B, and then assigns pin 4985 to flexibleinput-output logic B. In this example, output pin 4975 is not assignedto either flexible input-output A or flexible input-output B. As oneskilled in the art can appreciate, other methods of output pinassignment methods may be used for allocating output pins to flexibleinput-output logic.

FIG. 50 is a diagram showing a flexible input-output logic embodiment.Device 5000 includes input pins 5002, 5004, and 5006 which may beconnected to external peripheral devices to exchange information betweendevice 5000 and the peripheral devices. Device 5000 includes flexibleinput-output logic to dynamically assign pins 5002, 5004, and 5006 toeither input output controller (IOC) A 5030 or IOC B 5060. IOC A 5030and IOC B 5060 are similar to IOC A 4705 and IOC B 4710, respectively,that are shown in FIGS. 47A and 47B.

Flexible input-output controller 5065 configures flexible input-output A5010 and flexible input-output B 5040 using control lines 5070 through5095. Flexible input-output controller 5065 is similar to flexibleinput-output controller 4715 that is shown in FIGS. 47A and 47B. Inaddition, flexible input-output A 5010 and flexible input-output B 5040are similar to flexible input-output A 4720 and flexible input-output B4725, respectively, that are shown in FIGS. 47A and 47B. During flexibleinput-output logic configuration, flexible input-output controller 5065assigns each input pin (e.g. pins 5002-5006) to a particular IOC byeither enabling or disabling each control line. If pin 5002 should beassigned to IOC A 5030, flexible input-output controller 5065 enablescontrol line 5070 and disables control line 5075. This enables AND gate5015 and disables AND gate 5045. By doing this, information on pin 5002is passed to IOC A 5030 through AND gate 5015. If pin 5004 should beassigned to IOC A 5030, flexible input-output controller 5065 enablescontrol line 5080 and disables control line 5085. This enables AND gate5020 and disables AND gate 5050. By doing this, information on pin 5004is passed to IOC A 5030 through AND gate 5020. If pin 5006 should beassigned to IOC B 5060, flexible input-output controller 5065 enablescontrol line 5095 and disables control line 5090. This enables AND gate5055 and disables AND gate 5025. By doing this, information on pin 5006is passed to IOC B 5060 through AND gate 5055. As one skilled in the artcan appreciate, flexible input-output logic may be used for more or lessinput pins that are shown in FIG. 50 as well as output pinconfiguration. As one skilled in the art can also appreciate, othermethods of circuit design configuration may be used in flexibleinput-output logic to manage device interfaces.

In one embodiment, software code may be used instead of hardwarecircuitry to manage interface configurations. For example, a device mayload input and output information in a large look-up table anddistribute the information to particular interface pins based upon aparticular configuration.

While particular embodiments of the present invention have been shownand described, it will be obvious to those skilled in the art that,based upon the teachings herein, changes and modifications may be madewithout departing from this invention and its broader aspects and,therefore, the appended claims are to encompass within their scope allsuch changes and modifications as are within the true spirit and scopeof this invention. Furthermore, it is to be understood that theinvention is solely defined by the appended claims. It will beunderstood by those with skill in the art that if a specific number ofan introduced claim element is intended, such intent will be explicitlyrecited in the claim, and in the absence of such recitation no suchlimitation is present. For a non-limiting example, as an aid tounderstanding, the following appended claims contain usage of theintroductory phrases “at least one” and “one or more” to introduce claimelements. However, the use of such phrases should not be construed toimply that the introduction of a claim element by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim element to inventions containing only one such element,even when the same claim includes the introductory phrases “one or more”or “at least one” and indefinite articles such as “a” or “an”; the sameholds true for the use in the claims of definite articles.

1. A plurality of heterogeneous processors, comprising: one or morefirst processors that are adapted to process a first instruction set;one or more second processors that are adapted to process a secondinstruction set; and wherein the first processors and the secondprocessors share a memory.
 2. The plurality of heterogeneous processorsas described in claim 1 wherein at least one of the first processors isa PowerPC and wherein at least one of the second processor is asynergistic processing complex.
 3. The plurality of heterogeneousprocessors as described in claim 2 wherein each synergistic processingcomplex further includes: a synergistic processing unit; a localstorage; and a memory management unit, the memory management unitincluding a direct memory access controller.
 4. The plurality ofheterogeneous processors as described in claim 3 wherein the localstorage is shared with at least one of the first processors.
 5. Theplurality of heterogeneous processors as described in claim 1 furthercomprising: an operating system that runs on one of the firstprocessors, the first processor controlling a memory map thatcorresponds to the shared memory.
 6. The plurality of heterogeneousprocessors as described in claim 1 wherein the shared memory, the firstprocessors, and the second processors are located on a single substrate.7. The plurality of heterogeneous processors as described in claim 1further comprising: a common bus that interconnects the shared memory,the first processors, and the second processors.
 8. The plurality ofheterogeneous processors as described in claim 7 wherein the common busis an on-chip coherent multi-processor bus.
 9. The plurality ofheterogeneous processors as described in claim 1 further comprising: aplurality of interface controllers; a plurality of interface pins;flexible input-output logic that is adapted to assign one or moreinterface pins from the plurality of interface pins to one of theplurality of interface controllers.
 10. The plurality of heterogeneousprocessors as described in claim 9 wherein the assigning is managed byone of the first processors.
 11. The plurality of heterogeneousprocessors as described in claim 9 wherein the assigning is performed atsystem initialization.
 12. The plurality of heterogeneous processors asdescribed in claim 9 wherein the assigning is performed at system build.13. The plurality of heterogeneous processors as described in claim 1wherein each of the plurality of second processors is adapted to processa different instruction set.
 14. The plurality of heterogeneousprocessors as described in claim 13 wherein one of the second processorsis adapted to pass data to a different second processor using an on-chipcoherent multi-processor bus.
 15. The plurality of heterogeneousprocessors as described in claim 1 wherein the memory includes aplurality of regions and wherein at least one of the regions is selectedfrom the group consisting of an external system memory region, a localstorage aliases region, a TLB region, an MFC region, an operating systemregion, and an I/O devices region.
 16. The plurality of heterogeneousprocessors as described in claim 1 wherein at least one of the secondprocessors from the plurality of second processors uses private memory.17. A method for handling a plurality of heterogeneous processors thatshare a common memory, said method comprising: identifying a memory sizerequirement that corresponds to a first processor, the first processoradapted to process a first instruction set; configuring the commonmemory in response to the identification; determining whether there isunassigned memory located on the common memory after the configuration;and assigning the unassigned memory to a second processor, the secondprocessor adapted to process a second instruction set.
 18. The method asdescribed in claim 17 wherein the first processor is a Power PC andwherein the second processor is a synergistic processing unit.
 19. Themethod as described in claim 17 further comprising: managing the commonmemory using a common memory map.
 20. The method as described in claim19 wherein one of the first processors includes an operating systemwhereby the first processor controls the common memory map.
 21. Themethod as described in claim 19 wherein the common memory map includes aplurality of regions, wherein at least one of the regions is selectedfrom the group consisting of an external system memory region, a localstorage aliases region, a TLB region, an MFC region, an operating systemregion, and an I/O devices region.
 22. The method as described in claim17 wherein at least one of the second processors uses a direct memoryaccess controller for accessing the common memory.
 23. A computerprogram product stored on a computer operable media for handling aplurality of heterogeneous processors that share a common memory, saidcomputer program product comprising: means for identifying a memory sizerequirement that corresponds to a first processor, the first processoradapted to process a first instruction set; means for configuring thecommon memory in response to the identification; means for determiningwhether there is unassigned memory located on the common memory afterthe configuration; and means for assigning the unassigned memory to asecond processor, the second processor adapted to process a secondinstruction set.
 24. The computer program product as described in claim23 wherein the first processor is a Power PC and wherein the secondprocessor is a synergistic processing unit.
 25. The computer programproduct as described in claim 23 further comprising: means for managingthe common memory using a common memory map.
 26. The computer programproduct as described in claim 25 wherein one of the first processorsincludes an operating system whereby the first processor controls thecommon memory map.
 27. The computer program product as described inclaim 25 wherein the common memory map includes a plurality of regions,wherein at least one of the regions is selected from the groupconsisting of an external system memory region, a local storage aliasesregion, a TLB region, an MFC region, an operating system region, and anI/O devices region.
 28. The computer program product as described inclaim 23 wherein at least one of the second processors uses a directmemory access controller for accessing the common memory.